Quantum computing promise exponential speedups for a class of important problems. However, this potential can be realized only by large-scale quantum systems that operate on a large number of qubits. Unfortunately, to build a scalable quantum computer several challenges must be overcome, including the design of conventional computing and memory systems that can effectively interface with the quantum substrate while obeying the thermal and power constraints dictated by the quantum devices. In this, talk, I will discuss some of our recent work in addressing the design challenges for the control computer for scalable quantum computers.

First, I will discuss our QuEST architecture from MICRO-50 that deals with taming the instruction bandwidth of quantum computers via hardware-managed Error Correction. Qubits are fickle and require continuous error correction. This can require an instruction bandwidth that must scale linearly with the number of qubits and can limit the scalability if error correction is managed in software. QuEST delegates the task of error correction to the hardware and uses programmable microcode to reduce the instruction bandwidth requirements. Second, I will discuss the feasibility of using DRAM-based memory system for Quantum Computers. Quantum computers will require significant memory that can operate at cryogenic temperatures. We characterized commodity DRAM at cryogenic environments and examined the minimum operating temperatures and nature of faults. Finally, I will discuss our upcoming work at ASPLOS 2019 that exploits variation in device error rate to improve the overall reliability of near-term quantum computers.